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LTC2498
18
2498ff
applications inForMation
INPUT DATA FORMAT
The LTC2498 serial input word is 13 bits long and contains
two distinct sets of data. The first set (SGL, ODD, A2, A1,
A0) is used to select the input channel. The second set of
data(IM,FA,FB,SPD)isusedtoselectthefrequencyrejec-
tion,speedmode(1x,2x),andtemperaturemeasurement.
After power-up, the device initiates an internal reset cycle
whichsetstheinputchanneltoCH0–CH1(IN+=CH0,IN–=
CH1),thefrequencyrejectiontosimultaneous50Hz/60Hz,
and 1x output rate (auto-calibration enabled). The first
conversion automatically begins at power-up using this
default configuration. Once the conversion is complete,
a new word may be written into the device.
The first 3 bits shifted into the device consist of two preen-
able bits and one enable bit. As demonstrated in Figure 3,
the first three bits shifted into the device enable the device
configurationandinputchannelselection.Validsettingsfor
these three bits are 000, 100 and 101. Other combinations
should be avoided. If the first three bits are 000 or 100, the
following data is ignored (don’t care) and the previously
selected input channel and configuration remain valid for
the next conversion.
If the first 3 bits shifted into the device are 101, then the
next 5 bits select the input channel for the next conversion
cycle, see Table 3.
The first input bit following the 101 sequence (SGL)
determines if the input selection is differential (SGL = 0)
or single-ended (SGL = 1). For SGL = 0, two adjacent
channels can be selected to form a differential input. For
SGL = 1, one of 16 channels is selected as the positive
input.ThenegativeinputisCOMforallsingleendedopera-
tions. The remaining 4 bits (ODD, A2, A1, A0) determine
which channel(s) is/are selected and the polarity (for a
differential input).
The next serial input bit immediately following the input
channel selection is the enable bit for the conversion
configuration (EN2). If this bit is set to 0, then the next
conversion is performed using the previously selected
converter configuration. This is useful in systems using
the same rejection/speed for all input channels and for
backwardcompatibilitywiththeLTC2418/LTC2414families
of delta sigma ADCs.
A new configuration can be loaded into the device by
setting EN2 = 1, see Table 4. The first bit (IM) is used
to select the internal temperature sensor. If IM = 1, the
following conversion will be performed on the internal
temperaturesensorratherthantheselectedinputchannel.
The next 2 bits (FA and FB) are used to set the rejection
frequency. The final bit (SPD) is used to select either the
1x output rate if SPD = 0 (auto-calibration is enabled and
the offset is continuously calibrated and removed from
Table 2. Output Data Format
Differential Input Voltage
VIN*
Bit 31
EOC
Bit 30
DMY
Bit 29
SIG
Bit 28
MSB
Bit 27
Bit 26
Bit 25
…
Bit 0
VIN* ≥ 0.5 VREF**
0
1
0
…
0
0.5 VREF** – 1LSB
0
1
0
1
…
1
0.25 VREF**
0
1
0
1
0
…
0
0.25 VREF** – 1LSB
0
1/0***
0
1
…
1
0
1
0
…
0
–1LSB
0
1
…
1
–0.25 VREF**
0
1
0
…
0
–0.25 VREF** – 1LSB
0
1
0
1
…
1
–0.5 VREF**
0
1
0
…
0
VIN* < –0.5 VREF**
0
1
…
1
*The differential input voltage VIN = IN+ – IN–. **The differential reference voltage VREF = REF+ – REF–.
***The sign bit changes state during the 0 output code when the device is operating in the 2x speed mode.
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